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data sheet january 2005 fw802bf low-power phy 1394a-2000 two-cable transceiver/arbiter device ? ? distinguishing features ? compliant with ieee ? standard 1394a-2000, ieee s tandard for a high performance serial bus amendment 1. ? low power consumption during powerdown or microlow-pow er sleep mode. ? supports extended bias _handshake time for enhanced interoperabilit y with camcorders. ? while unpowered and connected to the bus, will not drive tpbias on a connected port even if receiving incoming bias voltage on that port. ? does not require external filter capacitors for pll. ? does not require a separate 5 v supply for 5 v link controller interoperability. ? interoperable across 1394 cable with 1394 physical layers (phy) using 5 v supplies. ? interoperable with 1394 link-l ayer controllers using 5 v supplies. ? 1394a-2000 compliant common mode noise filter on incoming tpbias. ? powerdown features to conserve energy in battery- powered applications include the following: ? device powerdown ball. ? link interface disable using lps. ? inactive ports power down. ? automatic microlow- power sleep mode during suspend. ? interface to link-layer controller supports annex j electrical isolation as we ll as bus-keeper isolation. features ? provides two fully compliant cable ports at 100 mbits/s, 200 mbits/s, and 400 mbits/s. ? fully supports 1394 open hci requirements. ? supports arbitrated shor t bus reset to improve utilization of the bus. ? supports ack-accelerated arbitration and fly-by con- catenation. ? supports connection debounce. ? supports multispeed packet concatenation. ? supports phy pinging and remote phy access packets. ? fully supports suspend/resume. ? supports phy-link interface initialization and reset. ? supports 1394a-2000 register set. ? supports lps/link-on as a part of phy-link inter- face. ? supports provisions of ieee 1394-1995 standard for a high performance serial bus . ? fully interoperable with firewire ? and i.link ? implementations of ieee 1394-1995. ? reports cable power fail interrupt when voltage at cps ball falls below 7.5 v. ? provides separate cable bi as and driver termination voltage supply for each port. other features ? 48-ball vtfsbgac package. ? single 3.3 v supply operation. ? data interface to link-layer controller provided through 2/4/8 parallel lines at 50 mbits/s. ? 25 mhz crystal oscillator and pll provide a 50 mhz link-layer controller clock as well as transmit/receive data at 100 mbits/s, 200 mbits/s, and 400 mbits/s. ? multiple separate package signals provided for ana- log and digital supplies and grounds. description the agere systems fw802bf device provides the analog physical layer functions needed to imple- ment a two-port node in a cable-based ieee 1394- 1995 and ieee 1394a-2000 network. each cable port incorporates two differential line transceivers. the transceiv ers include circuitry to monitor the line conditions as needed for determin- ing connection status, for initialization and arbitration, and for packet reception and transmis- sion. the phy is designed to interface with a link- layer controller (llc).
2 2 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 table of contents contents page distinguishing features ....................................................................................................... ..................................... 1 features ...................................................................................................................... ............................................. 1 other features ................................................................................................................ .........................................1 description ................................................................................................................... ............................................. 1 ball information .............................................................................................................. .......................................... 6 signal information ..................................... ....................................................................... ......................................... 7 application information ....................................................................................................... .................................... 11 crystal selection considerations .............................................................................................. .............................. 12 load capacitance .............................................................................................................. .............................. 13 adjustment to crystal loading ................................................................................................. ........................ 13 crystal/board layout .......................................................................................................... ............................. 13 absolute maximum ratings ................................ ...................................................................... .............................. 14 electrical characteristics .... ................................................................................................ .................................... 15 timing characteristics ........................................................................................................ .................................... 18 timing waveforms ........................................... ................................................................... .................................... 19 internal register conf iguration ............................................................................................... ................................ 20 outline diagrams .............................................................................................................. ...................................... 25 48-ball tfsbgac ............................................................................................................... ............................. 25 ordering informat ion .......................................................................................................... ..................................... 25 list of figures figures page figure 1. block diagram ........................................................................................................ ................................... 5 figure 2. fw802bf ball diagram (4 8-ball tfsbgac) top view ...................................................................... ...... 6 figure 3. typical external com ponent connections ............................................................................... ............... 11 figure 4. typical port termin ation network .................................................................................... ...................... 12 figure 5. crystal circuitry .... ................................................................................................ ................................... 13 figure 6. dn, ctln, and lreq input setup and hold ti mes waveforms ............................................................. 19 figure 7. dn, ctln output delay relative to sysclk wave forms................................................................... .... 19 list of tables tables page table 1. fw802bf (48-ball tfsbgac) ball coordinatio n table .................................................................... ........ 6 table 2. signal descriptions................................................................................................... .................................. 7 table 3. absolute maximum ratings .................. ........................................................................... ......................... 14 table 4. analog characteristics ....................... ........................................................................ ............................... 15 table 5. driver characteristics ............................................................................................... ................................ 16 table 6. device characteristics ............................................................................................... ............................... 17 table 7. switching characteristics ............................................................................................ ............................. 18 table 8. clock characteristics ..................... .......................................................................... ................................ 18 table 9. phy register map for the cable environmen t .......................................................................... .............. 20 table 10. phy register fields for the cable enviro nment ....................................................................... ............. 20 table 11. phy register page 0: port status page ............................................................................... ................ 22 table 12. . phy register port status page fields ............................................................................. ................... 23 table 13. phy register page 1: vendor identification page ................................................................... ............ 24 table 14. phy register vendor identification page fi elds ..................................................................... .............. 24
data sheet fw802bf phy 1394a-2000 january 2005 two-cable transceiver/arbiter device agere systems inc. 3 description (continued) the phy requires either an external 24.576 mhz crys- tal or crystal oscillator. the internal oscillator drives an internal phase-locked loop (pll) that generates the required 393.216 mhz reference signal. the 393.216 mhz reference signal is internally divided to provide the 49.152 mhz, 98.304 mhz, and 196.608 mhz clock signals that control transmission of the outbound encoded strobe and data information. the 49.152 mhz clock signal is also supplied to the associated llc for synchronization of the two chips and is used for resyn- chronization of the received data. the powerdown function, when enabled by the pd signal high, stops operation of the pll and disables all circuitry except the cable-not-active (cna) signal circuitry. the phy supports an isolation barrier between itself and its llc. when ison is tied high, the link interface outputs behave normally. when ison is tied low, inter- nal differentiating logic is enabled, and the outputs become short pulses that can be coupled through a capacitor or transformer as described in the ieee 1394-1995 annex j. to operate with bus-keeper isolation, the ison ball of the fw802bf must be tied high. data bits to be transmitted through the cable ports are received from the llc on two, four, or eight data lines (d[0:7]), and are latched internally in the phy in syn- chronization with the 49.1 52 mhz system clock. these bits are combined serially, encoded, and transmitted at 98.304 mbits/s, 196.608 mbit s/s, or 393.216 mbits/s as the outbound data-strobe in formation stream. during transmission, the encoded data information is transmit- ted differentially on the tpa and tpb cable pair(s). during packet reception, the tpa and tpb transmit- ters of the receiving cable port are disabled and the receivers for that port are enabled. the encoded data information is received on the tpa and tpb cable pair. the received data-strobe information is decoded to recover the receive clock signal and the serial data bits. the serial data bits ar e split into two (for s100), four (for s200), or eight (for s400) parallel streams, resynchronized to the local s ystem clock, and sent to the associated llc. the received data is also trans- mitted (repeated) out of the other active (connected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states dur- ing initialization and arbitration. the outputs of these comparators are used by the internal logic to deter- mine the arbitration status . the tpa channel monitors the incoming cable common-mode voltage. the value of this common-mode voltage is used during arbitra- tion to set the speed of t he next packet transmission. in addition, the tpb channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. this moni- tor is called bias-detect. the tpbias circuit monitors the value of incoming tpa pair common-mode voltage when local tpbias is inactive. because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. this monitor is called connect-detect. both the tpb bias-detect monitor and tpbias con- nect-detect monitor are used in suspend/resume signaling and cable connection detection. the phy provides a 1.86 v nominal bias voltage for driver load termination. when seen through a cable by a remote receiver, this bias voltage indicates the pres- ence of an active connection. the value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 v or 3 v nominal supplies. this bias voltage source should be stabilized by using an extern al filter capacitor of approximately 0.33 f. the transmitter circuitry, the receiver circuitry, and the twisted-pair bias voltage circuity are all disabled with a powerdown condition. the powerdown condition occurs when the pd input is high. the port transmitter circuitry, the receiver circuitry, and the tpbias output are also disabled when the port is disabled, sus- pended, or disconnected. the line drivers in the phy operate in a high-imped- ance current mode and are designed to work with external 112 ? line-termination resistor networks. one network is provided at each end of each twisted-pair cable. each network is composed of a pair of series- connected 56 ? resistors. the midp oint of the pair of resistors that is directly co nnected to the twisted-pair a (tpa) signals is connected to the tpbias voltage sig- nal. the midpoint of the pair of resistors that is directly connected to the twisted-pair b (tpb) signals is cou- pled to ground through a parallel rc network with recommended resistor and capacitor values of 5 k ? and 220 pf, respectively. the value of the external resistors are specified to meet the ieee 1394 stan- dard specifications when connected in parallel with the internal receiver circuits. the driver output current, along with other internal operating currents, is set by an external resistor. this resistor is connected betw een the r0 and r1 signals and has a value of 2.49 k ? 1%.
fw802bf phy 1394a-2000 data sheet two-cable transceiver/ar biter device january 2005 4 agere systems inc. description (continued) the fw802bf supports suspend/resume as defined in the ieee 1394a-2000 specif ication. the suspend mechanism allows an fw802bf port to be put into a suspended state. in this state, a port is unable to transmit or receive data pa ckets, however, it remains capable of detecting conn ection status changes and detecting incoming tpbias. when all ports of the fw802bf are suspended, all circuits except the bias voltage reference generator , and bias detection cir- cuits are powered down, resu lting in significant power savings. the use of suspend/resume is recommended. as an input, the c_lkon signal indicates whether a node is a contender for bus manager. when the c_lkon signal is asserted, it means the node is a contender for bus manager. when the signal is not asserted, it means that th e node is not a contender. the c bit corresponds to bit 20 in the self-id packet (see section 4.3. 4.1 of the ieee 1 394a-2000 st andard for additional details). the power-class (pwr_class) bi ts of the self-id packet have a default value of 0, i.e., power-class 000. these bits can be read and modified through the llc using figure 5b-1 (phy register map) and section 4.3.4.1 of the ieee 1394a-2000 standard. see table 9 of this document for the address space of the pwr_class register. a powerdown signal (pd) is provided to allow a power- down mode where most of the phy circuits are powered down to conserve energy in battery-powered applications. the internal lo gic in fw802bf is reset as long as the powerdown signal is asserted. a cable sta- tus signal (cna) provides a high output when none of the twisted-pair cable port s are receiving incoming bias voltage. this output is not debounced. the cna output can be used to determine when to power the phy down or up. in the powerdown mode, all circuitry is disabled except the cna ci rcuitry. it should be noted that when the device is powered down, it does not act in a repeater mode. when the power supply of the phy is removed while the twisted-pair cables are connected, the phy trans- mitter and receiver circuitry is designed to present a high impedance to the cable in order to not load the tpbias signal voltage on t he other end of the cable. whenever the tba/tpb signals are wired to a con- nector, they must be term inated using the normal termination network (see figure 4.). this is required for reliable operation. for those applications, when one of the fw802bf?s ports is not wired to a connec- tor, those unused ports may be left unconnected without normal termination. when a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. note: all gap counts on all nodes of a 1394 bus must be identical. the software accomplishes this by issuing phy configuration packets (see section 4.3.4.3 of the ieee 1394a-2000 standard) or by issuing two bus resets, which resets the gap counts to the maximum level (3fh). the link power status (lps) signal works with the c_lkon signal to manage the llc power usage of the node. the lps signal indicates that the llc of the node is powered up or powered down. if lps is inac- tive for more than 1.2 ms and less than 25 ms, the phy/link interface is reset. if lps is inactive for greater than 25 ms, the phy will disable the phy/link inter- face to save power. fw802bf continues its repeater function even when the phy/lin k interface is disabled. if the phy then receives a link-on packet, the c_lkon signal is activated to outp ut a 6.114 mhz signal that can be used by the llc to power itself up. once the llc is powered up, the lps signal communicates this to the phy and the phy/link interface is enabled. the c_lkon signal is turned off when lps is active or when a bus reset occurs, provided the interrupt that caused c_lkon is not present. when the phy/link interface is in the disabled state, the fw802bf will automati cally enter a low-power mode if all ports are inactive (disconnected, disabled, or suspended). in this low-power mode, the fw802bf disables its pll and also disables parts of its reference circuitry depending on the state of the ports (some reference circuitry must remain active in order to detect incoming tp bias). the lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports interrupt enable bit (see table 12) cleared. the fw802b f will exit the low-power mode when the lps input is asserted high or when a port event occurs that requires the fw802bf to become active in order to respond to the event or to notify the llc of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). when the fw802bf is in the low-power mode, the sysclk output will become active (and the phy/link interface will be initialized and become operative) within 3 ms after l ps is asserted high. two of the fw802bf?s signals are used to set up various test conditions used only during the device manufacturing process. these signals (se and sm) should be connected to vss for normal operation.
agere systems inc. 5 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 description (continued) 5-5459.f (f) r.3 figure 1. block diagram link interface i/o received data decoder/ arbitration and control retimer state machine logic bias voltage and current generator cable port 1 oscillator, pll system, and clock generator transmit data encoder cable port 0 tpa[0] tpan[0] tpb[0] tpbn[0] tpbias[0] tpbias[1] tpa[1] tpan[1] tpb[1] tpbn[1] xi xo cps lps ison cna sysclk lreq ctl[0] ctl[1] d[0] d[1] d[2] d[3] c_lkon se sm pd resetn crystal d[4] d[5] d[6] d[7] r[0] r[1]
6 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 ball information note: refer to the outline drawing on page 25 for a bottom view. 5-8117 figure 2. fw802bf ball diagram (48-ball tfsbgac) top view table 1. fw802bf (48-ball tfsbgac) ball coordination table ball number ball name ball number ball name ball number ball name ball number ball name a1 ctl[0] b5 v dd e1 d[5] g5 v ss a2 lreq b6 r[1] e2 d[3] g6 v ss a3 sysclk b7 v ssa e7 se g7 v dda a4 xo b8 tpa[1] e8 tpbn[1] g8 tpan[0] a5 xi c1 d[1] f1 d[7] h1 cna a6 v ss c2 d[0] f2 d[4] h2 v dd a7 r[0] c7 v dda f7 v ssa h3 pd a8 tpbias[1] c8 tpan[1] f8 tpa[0] h4 ison b1 ctl[1] d1 d[2] g1 lps h5 cps b2 resetn d2 v dd g2 d[6] h6 sm b3 v ss pll d7 tpbias[0] g3 v ss h7 tpb[0] b4 v dd pll d8 tpb[1] g4 c_lkon h8 tpbn[0] a b c d e f g h a b c d e f g h 1 2 3 4 5 6 7 8 a1 ball pad corner 1 2 3 4 5 6 7 8
agere systems inc. 7 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 signal information table 2. signal descriptions ball number signal * type name/description g4 c_lkon i/o bus manager capable input and link-on output. on hardware reset (resetn), this ball is used to set the default value of the contender status indicated during self-id. the bit value programming is done by tying the signal through a 10 k ? resistor to v dd (high, bus manager capable) or to gnd (low, not bus manager capable). using either the pull-up or pull- down resistor allows th e link-on output to override the input value when necessary. after hardware reset, this ball is set as an output. if the lps is inactive, c_lkon indicates one of the followin g events by asserting a 6.114 mhz signal. 1. fw802bf receives a link-on packet addressed to this node. 2. port_event register bit is 1. 3. any of the timeout, pwr_fail, or loop register bits are 1 and the watchdog register bit is also 1. 4. once activated, the c_lkon output will contin ue active until the lps becomes active. the phy also deasserts the c_lkon output when a 1394 bus reset occurs, if the c_lkon is active due solely to the recep- tion of a link-on packet. note: if an interrupt condition exists whic h would otherwise cause the c_lkon output to be activated if the lps were inactive, the c_lkon output will be activated when the lps subsequently becomes inactive. h1 cna o cable-not-active output. cna is asserted high when none of the phy ports are receiving an incoming bias voltage. this circuit remains active during the powerdown mode. h5 cps i cable power status. cps is normally connected to the cable power through a 400 k ? resistor. this circuit drives an internal comparator that detects the presence of cable power. this information is maintained in one internal register and is available to the llc by way of a register read (see table 9, address register 0000 2 , bit 7/ps). in applications that do not sink or source 1394 power (vp), this ball can be tied to ground. note: when this ball is grounded, the pwr_fail bit in phy register 0101 2 will be set. a1 ctl[0] i/o control i/o. the ctln signals are bidirectional communications control signals between the phy and the llc. these signals control the passage of information between the two devices. bus-keeper circuitry is built into these terminals. b1 ctl[1] c1, c2, d1, e1, e2, f1, f2, g2 d[0:7] i/o data i/o. the dn signals are bidirectiona l and pass data between the phy and the llc. bus-keeper circuitry is built into these terminals. * active-low signals are indicated by ?n? at the end of signal names, within this document.
8 8 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 signal information (continued) table 2. signal descriptions (continued) ball number signal * type name/description h4 ison i link interface isolation disable input (active-low). ison controls the operation of an internal pulse di fferentiating function used on the phy-llc interface signals, ctln and dn, when they operate as outputs. when ison is asserted low, the isolation barrier is implemented between phy and its llc (as described in annex j of ieee 1394-1995). ison is normally tied high to disable isolation differentiation. bus-keepers are enabled when ison is high (inactive) on ctln, dn, and lreq. when ison is low (active), the bus-keepers are disabled. please refer to agere?s application note, 1394 isolation (ap05-014cmpr), for more information. g1 lps i link power status. lps is connected to either the v dd supplying the llc or to a pulsed output that is acti ve when the llc is powered for the purpose of monitoring the llc power status. if lps is inactive for more than 1.2 s and less than 25 s, the phy-link interface is reset. if lps is inactive for greater than 25 s, the phy will disable the phy/link interface to save power. fw802bf continues its repeater function. a2 lreq i link request. lreq is an output from the llc that requests the phy to perform some service. bus-keeper circuitry is built into this terminal. h3 pd i powerdown. when asserted high, pd turns off all internal circuitry except the bias-detect circuits that drive t he cna signal. internal fw802bf logic is kept in the reset state as long as pd is asserted. the pd terminal is provided for backward compatibility. it is recommended that the fw802bf be allowed to manage its own power consumption using suspend/resume in conjunction with lps. c_lkon features are defined in the ieee 1394a- 2000 specification. b4 v dd pll ? power for pll circuit. v dd pll supplies power to the pll circuitry portion of the device. b3 v ss pll ? ground for pll circuit. v ss pll is tied to a low-impedance ground plane. a7 r[0] i current setting resistor. an internal reference voltage is applied to a resistor connected between r0 and r1 to set the operating current and the cable driver output current. a low temperature-coefficient resistor (tcr) with a value of 2.49 k ? 1% should be used to meet the ieee 1394-1995 standard requirements for output voltage limits. b6 r[1] b2 resetn i reset (active-low). when resetn is asserted low (active), a 1394 bus reset condition is set on the active cable ports and the fw802bf is reset to the reset start state. to guarantee that the phy will reset, this ball must be held low for at least 2 ms. an inte rnal pull-up resistor connected to v dd is provided so that only an external delay capacitor (0.1 f) and resistor (510 k ? ) in parallel, are required to connect this ball to ground. this circuitry will ensure that the capacito r will be discharged when phy power is removed. the input is a standard logic buffer and can also be driven by an open-drain logic output buffer. do not leave this ball unconnected. e7 se i test mode control. se is used during agere?s manufacturing test and should be tied to v ss for normal operation. * active-low signals are indicated by ?n? at the end of signal names, within this document.
agere systems inc. 9 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 h6 sm i test mode control. sm is used during agere?s manufacturing test and should be tied to v ss for normal operation. a3 sysclk o system clock. sysclk provides a 49.152 mh z clock signal, which is syn- chronized with the data transfers to the llc. f8 tpa[0] analog i/o port0, port cable pair a. tpa0 is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802bf?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-de tect circuitry will keep the port in a disconnected state. g8 tpan[0] b8 tpa[1] analog i/o port1, port cable pair a. tpa1 is the port a connection to the twisted- pair cable. board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the exter- nal load resistors and to the cable connector. when the fw802bf?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. internal conn ect-detect circuitry will keep the port in a discon- nected state. c8 tpan[1] h7 tpb[0] analog i/o port0, port cable pair b. tpb0 is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802bf?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-detect circui try will keep the port in a disconnected state. h8 tpbn[0] d8 tpb[1] analog i/o port1, port cable pair b. tpb1 is the port b connection to the twisted- pair cable. board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. when the fw802bf?s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. internal connect-detect circui try will keep the port in a disconnected state. e8 tpbn[1] d7 tpbias[0] analog i/o portn, twisted-pair bias. (where n refers to the port number) tpbias provides the 1.86 v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable con- nection signal to the remote nodes. when the fw802bf?s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. inter- nal connect-detect circuitry will k eep the port in a disconnected state. a8 tpbias[1] b5, d2, h2 v dd ? digital power. v dd supplies power to the digital portion of the device. signal information (continued) table 2. signal descriptions (continued) ball number signal * type name/description * active-low signals are indicated by ?n? at the end of signal names, within this document.
10 10 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 c7, g7 v dda ? analog circuit power. v dda supplies power to the analog portion of the device. a6, g3, g5, g6 v ss ? digital ground. all v ss signals should be tied to the low-impedance ground plane. b7, f7 v ssa ? analog circuit ground. all v ssa signals should be tied together to a low- impedance ground plane. a5 xi ? crystal oscillator. xi and xo connect to a 24.576 mhz parallel resonant fundamental mode crystal. although, when a 24.576 mhz clock source is used, it can be connected to xi with xo left unconnected. the optimum val- ues for the external load capacitors and resistor are dependent on the specifications of the crystal used. it is necessary to add an external series resistor (r l ) to the xo pin (see figures 3 and 5). for more details, refer to the crystal selection considerations secti on in this data sheet. note that it is very important to place the crystal as close as possible to the xo and xi pins, i.e., within 0.5 in./1.27 cm. a4 xo signal information (continued) table 2. signal descriptions (continued) ball number signal * type name/description * active-low signals are indicated by ?n? at the end of signal names, within this document.
agere systems inc. 11 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 application information * see figure 4 for typical port termination network. figure 3. typical external component connections tpbias[1] tpa[1] tpan[1] tpb[1] tpbn[1] tpa[0] tpan[0] tpbn[0] r[0] vssa tpbias[0] se vss vdda tpb[0] sm vss r[1] vss xi xo syscl lreq ctl[0] ctl[1 d[1] d[2] d[5] d[7] lps cna reset vsspll vddpll vdd d[0] vdd d[3] d[4] d[6] vss c_lkon vss vdd pd ison cps vdda 24.576 mhz 2.49 k ? port 1* port 0* 400 k ? cable power 0.1 f a1 ball agere fw802bf lcc pulse or v dd llc port 0* pad corner port 0* llc llc llc llc llc llc 510 k ? c l c l rl
12 12 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 application information (continued) 5-6930 (f) figure 4. typical port termination network crystal selection considerations the fw802bf is designed to use an external 24.576 mh z parallel resonant fundamental mode crystal connected between the xi and xo terminals to provide the re ference for an internal oscillator circuit. the ieee 1394a-2000 standard requires that fw802bf have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. to achieve this, it is re commended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. the total frequency variation must be kept below 100 ppm from nominal with some allowance for error intro- duced by board and device variations . trade offs between frequency tolera nce and stability may be made as long as the total frequency variation is less than 100 ppm. tpbias[1] tpa[1] tpan[1] tpb[1] tpbn[1] tpbias[0] tpa[0] tpan[0] tpb[0] tpbn[0] tpbias[1] 56 ? 56 ? 56 ? 56 ? 5 k ? 220 pf 0.33 f ieee 1394-1995 standard connector use same port termination network as illustrated below. 1 3 5 2 4 6 vg vp cable power a8 b8 c8 d8 e8 d7 f8 g8 h7 h8
agere systems inc. 13 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 crystal selection considerations (continued) load capacitance the frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. total load capacitance (c l ) is a function of not only the discrete load capacitors, but also capacitances from the fw802bf board traces and capacitances of the other fw802bf connected components. the values for load capacitors (c a and c b ) should be calculated using this formula: c a = c b = (cl ? cstray) 2 where: c l = load capacitance specified by the crystal manufacturer. cstray = capacitance of the board a nd the fw802bf, typically 2 pf?3 pf. r l = load resistance; the value of r l is dependent on the specific crystal used. please refer to your crystal manufacturer?s data sheet and application notes to determine an appropriate value. figure 5. crystal circuitry adjustment to crystal loading the resistor (r l ) in figure 5 is recommended for fine-tuning the crys tal circuit. the value for this resistor is depen- dent on the specific crystal used. please refer to your crystal manufacturer?s data sheet and application notes to determine an appropriate value for r l . a more precise value for this resistor can be obtained by placing different values of r l on a production bo ard and using an oscilloscope to view the resultant clock wavefo rm at node a for each resistor value. the desired wave form should have the following characte ristics: the waveform should be sinu- soidal, with an amplitude as large as possible, but not greater than 3.3 v or less than 0 volts. crystal/board layout the layout of the crystal portion of the phy circuit is important for obtaining the correct frequency and minimizing noise introduced into the fw802bf pll. the crystal and two load capacitors (c a + c b ) should be considered as a unit during layout. they should be placed as close as possible to one another, while minimizing the loop area cre- ated by the combination of the three components. minimi zing the loop area minimizes the effect of the resonant current that flows in this resonant circ uit. this layout unit (crystal and load capacitors) should then be placed as close as possible to the phy xi and xo terminals to mini mize trace lengths. vias should not be used to route the xi and xo signals. 1394 application suppor t contact information e-mail: support1394@agere.com c b c a xi xo r l a
14 14 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sect ions of the data sheet. exposure to absolute maximum ratings for extended periods can adversely af fect device reliability. table 3. absolute maximum ratings * except for 5 v tolerant i/o (ctl0, ctl1, d0?d7, and lreq) where v i max = 5.5 v. parameter symbol min max unit supply voltage range v dd 3.0 3.6 v input voltage range* v i ?0.5 v dd + 0.5 v output voltage range at any output v o ?0.5 v dd + 0.5 v operating free air temperature t a 070 c storage temperature range t stg ?65 150 c
agere systems inc. 15 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 electrical characteristics table 4. analog characteristics parameter test conditions symbol min typ max unit supply voltage source power node v dd?sp 3.0 3.3 3.6 v differential input voltage cable inputs, 100 mbits/s operation v id?100 142 ? 260 mv cable inputs, 200 mbits/s operation v id?200 132 ? 260 mv cable inputs, 400 mbits/s operation v id?400 100 ? 260 mv cable inputs, during arbitration v id?arb 168 ? 265 mv common-mode voltage source power mode tpb cable inputs, speed signaling off v cm 1.165 ? 2.515 v tpb cable inputs, s100 speed signaling on v cm?sp?100 1.165 ? 2.515 v tpb cable inputs, s200 speed signaling on v cm?sp?200 0.935 ? 2.515 v tpb cable inputs, s400 speed signaling on v cm?sp?400 0.532 ? 2.515 v common-mode voltage nonsource power mode* * for a node that does not source power (see section 4.2.2.2 in ieee 1394-1995 standard). tpb cable inputs, speed signaling off v cm 1.165 ? 2.015 v tpb cable inputs, s100 speed signaling on v cm?nsp?100 1.165 ? 2.015 v tpb cable inputs, s200 speed signaling on v cm?nsp?200 0.935 ? 2.015 v tpb cable inputs, s400 speed signaling on v cm?nsp?400 0.532 ? 2.015 v receive input jitter tpa, tpb cable inputs, 100 mbits/s operation ???1.08ns tpa, tpb cable inputs, 200 mbits/s operation ???0.5ns tpa, tpb cable inputs, 400 mbits/s operation ???0.315ns receive input skew between tpa and tpb cable inputs, 100 mbits/s operation ???0.8ns between tpa and tpb cable inputs, 200 mbits/s operation ???0.55ns between tpa and tpb cable inputs, 400 mbits/s operation ???0.5ns positive arbitration comparator input threshold voltage ?v th +89?168mv negative arbitration comparator input threshold voltage ?v th ? ?168 ? ?89 mv speed signal input threshold voltage 200 mbits/s v th?s200 45 ? 139 mv 400 mbits/s v th?s400 266 ? 445 mv output current tpbias outputs i o ?5 ? 2.5 ma tpbias output voltage at rated i/o current v o 1.665 ? 2.015 v current source for connect detect circuit ?i cd ??76 a
16 16 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 electrical characteristics (continued) table 5. driver characteristics parameter test conditions symbol min typ max unit differential output voltage 56 ? load v od 172 ? 265 mv off-state common-mode voltage drivers disabled v off ??20mv driver differential current, tpa, tpan, tpb, tpbn driver enabled, speed signaling off* * limits are defined as the algebraic sum of tpa and tpan driver currents. limits al so apply to tpb and tpbn as the algebraic s um of driver currents. ? limits are defined as the absolute limi t of each of tpb and tpbn driver currents. i diff ? 1.05 ? 1.05 ma common-mode speed signaling current, tpb, tpbn 200 mbits/s speed signaling enabled ? i sp ? 2.53 ? ? 4.84 ma 400 mbits/s speed signaling enabled ? i sp ? 8.1 ? ? 12.4 ma
agere systems inc. 17 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 electrical characteristics (continued) table 6. device characteristics * device is capable of both differentiated and undifferentiated operation. parameter test conditions symbol min typ max unit supply current: one port active all ports active no ports active, (microlow- power sleep mode) lps = 0 pd = 1 v dd = 3.3 v i dd i dd i dd i dd ? ? ? ? 54 74 50 50 ? ? ? ? ma ma a a high-level output voltage i oh max, v dd = min v oh v dd ? 0.4 ? ? v low-level output voltage i ol min, v dd = max v ol ??0.4v high-level input voltage cmos inputs v ih 0.7 v dd ?? v low-level input voltage cmos inputs v il ? ? 0.2 v dd v pull-up current, resetn input v i = 0 v i i 11 ? 32 a powerup reset time, resetn input v i = 0 v ? 2 ? ? ms rising input threshold voltage resetn input ?vi rst 1.1 ? 1.4 v output current sysclk i ol /i oh @ ttl ?16 ? 16 ma control, data i ol /i oh @ cmos ?12 ? 12 ma cna i ol /i oh ?16 ? 16 ma c_lkon i ol /i oh ?2 ? 2 ma input current, lreq, lps, pd, se, sm, pc[0:2] inputs v i = v dd or 0 v i i ?? 1 a off-state output current, ctl[0:1], d[0:7], c_lkon i/os v o = v dd or 0 v i oz ?? 5 a power status input threshold voltage, cps input 400 k ? resistor v th 7.5 ? 8.5 v rising input threshold voltage*, lreq, ctln, dn ?v it +v dd /2 + 0.3 ? v dd /2 + 0.8 v falling input threshold voltage*, lreq, ctln, dn ?v it ? v dd /2 ? 0.8 ? v dd /2 ? 0.3 v bus holding current, lreq, ctln, dn v i = 1/2(v dd ) ? 250 ? 550 a rising input threshold voltage lps ?v lih ? ? 0.24 v dd + 1 v falling input threshold voltage lps ?v lil 0.24 v dd + 0.2 ? ? v
18 18 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 timing characteristics table 7. switching characteristics table 8. clock characteristics symbol parameter measured test conditions min typ max unit ? jitter, transmit tpa, tpb ? ? ? 0.15 ns ? transmit skew between tpa and tpb ??? 0.1 ns t r rise time, transmit (tpa/tpb) 10% to 90% r i = 56 ?, c i = 10 pf ??1.2ns t f fall time, transmit (tpa/tpb) 90% to 10% r i = 56 ?, c i = 10 pf ??1.2ns t su setup time, dn, ctln, lreq to sysclk 50% to 50% see figure 6. 6 ? ? ns t h hold time, dn, ctln, lreq from sysclk 50% to 50% see figure 6. 0 ? ? ns t d delay time, sysclk to dn, ctln 50% to 50% see figure 7. 1 ? 6 ns parameter symbol min typ max unit external clock source frequency f 24.5735 24.5760 24.5785 mhz
agere systems inc. 19 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 timing waveforms 5-6017.a (f) figure 6. dn, ctln, and lreq input setup and hold times waveforms 5-6018.a (f) figure 7. dn, ctln output de lay relative to sysclk waveforms sysclk dn, ctln, lreq tsu th sysclk dn, ctln td
20 20 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 internal register configuration the phy register map is shown below in table 9. (refer to ieee 1394a-2000, 5b.1 for more information.) table 9. phy register map for the cable environment the meanings of the register fields within the phy regi ster map are defined by table 10 below. power reset values not specified are resolved by the operation of the phy state machines subs equent to a power reset. table 10. phy register fields for the cable environment address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0000 2 physical_id r ps 0001 2 rhb ibr gap_count 0010 2 extended (7) xxxxx to ta l _ p o r ts 0011 2 max_speed xxxxx delay 0100 2 lctrl contender jitter pwr_class 0101 2 watchdog isbr loop pwr_fail timeout port_event enab_accel enab_multi 0110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 0111 2 page_select xxxxx port_select 1000 2 register 0 page_select 1111 2 register 7 page_select required xxxxx reserved field size type power reset value description physical_id 6 r 000000 the address of this node determined during self-identification. a value of 63 indicates a malconfigur ed bus; the link will not transmit any packets. r 1 r 0 when set to one, indicates that this node is the root. ps 1 r ? cable power active. rhb 1 rw 0 root hold-off bit. w hen set to one, the force_root variable is true, which instructs the phy to attempt to become the root during the next tree identify process. ibr 1 rw 0 initiate bus reset . when set to one, instructs the phy to set ibr true and reset_time to reset_t ime. these values in turn cause the phy to initiate a bus reset without arbitration; the reset signal is asserted for 166 s. this bit is self-clearing. gap_count 6 rw 3f 16 used to configure the arbitration ti mer setting in order to optimize gap times according to the topol ogy of the bus. se e section 4.3.6 of ieee standard 1394a-2000 for the encoding of this field. extended 3 r 111 this field has a constant value of seven, wh ich indicates the extended phy register map.
agere systems inc. 21 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 internal register configuration (continued) table 10. phy register fields for the cable environment (continued) field size type power reset value description total_ports 4 r 0010 the number of ports implemented by this phy. this count reflects the number. max_speed 3 r 010 indicates the speed(s) this phy supports: 000 2 = 98.304 mbits/s 001 2 = 98.304 and 196.608 mbits/s 010 2 = 98.304, 196.608, and 393.216 mbits/s 011 2 = 98.304, 196.608, 393.216, and 786.43 mbits/s 100 2 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 mbits/s 101 2 = 98.304, 196.608, 393.216 , 786.432, 1,572.864, and 3,145.728 mbits/s all other values are reserved for future definition. delay 4 r 0000 worst-case repeater delay, expressed as 144 + (delay * 20) ns. lctrl 1 rw 1 link active. cleared or set by software to control the value of the l bit transmitted in the node? s self-id packet 0, which will be the logical and of this bit and lps active. contender 1 rw see description. cleared or set by software to control the value of the c bit transmitted in the self-id packet. powerup reset value is set by c_lkon ball. jitter 3 r 000 the difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. pwr_class 3 rw 000 power class. controls th e value of the pwr field transmitted in the self-id packet. see section 4.3.4.1 of ieee standard 1394a-2000 for the encoding of this field. watchdog 1 rw 0 when set to o ne, the phy will set port_eve nt to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bu s reset. a write of one to this bit instructs the phy to set isbr true and reset_time to short_reset_time. these values in turn cause the phy to arbitrate and issue a short bus reset. this bit is self-clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 1 cable power failure detect. set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero. timeout 1 rw 0 arbitration state machine timeout. a write of one to this bit clears it to zero (see max_arb_state_time). port_event 1 rw 0 port event detect. the phy sets this bit to one if any of con- nected, bias, disabled, or fault change for a port whose int_enable bit is one. the phy also sets this bit to one if resume operations commence for any port and watchdog is one. a write of one to this bit clears it to zero.
22 22 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 internal register configuration (continued) table 10. phy register fields for the cable environment (continued) the port status page is used to access configuration and status information fo r each of the phy?s ports. the port is selected by writing zero to page_select and the desired po rt number to port_select in the phy register at address 0111 2 . the format of the port status page is illustrated by table 11 below; reserved fields are shown shaded. the meanings of the register fields with the port status page are defined by table 12. table 11. phy register page 0: port status page field size type power reset value description enab_accel 1 rw 0 enable arbitr ation acceleration. when set to one, the phy will use the enhancements specified in section 4.4 of 1394a-2000 specifi- cation. phy behavior is unspecified if the value of enab_accel is changed while a bus request is pending. enab_multi 1 rw 0 enable multispeed packet co ncatenation. when set to one, the link will signal the speed of all packets to the phy. page_select 3 rw 000 selects which of eight po ssible phy register pages are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. port_select 4 rw 0000 if the page selected by page_select presents per-port information, this field selects which port?s registers are accessible through the window at phy register addresses 1000 2 through 1111 2 , inclusive. ports are numbered monotonically starting at zero, p0. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 astat bstat child connected bias disabled 1001 2 negotiated_speed int_enable fault xxxxx xxxxx xxxxx 1010 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1011 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1100 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1101 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1110 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1111 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx required xxxxx reserved
agere systems inc. 23 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 internal register configuration (continued) the meanings of the register fields with the por t status page are defined by table 12 below. table 12. phy register port status page fields field size type power reset value description astat 2 r ? tpa line state for the port: 00 2 = invalid 01 2 = 1 10 2 = 0 11 2 = z bstat 2 r ? tpb line state for the port (same encoding as astat). child 1 r 0 if equal to one, the port is a child; otherwise, a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy transitions to state t1: child hand- shake during the tree identify process (see section 4.4.2.2 in ieee standard 1394-1995). connected 1 r 0 if equal to one, the port is connected. bias 1 r 0 if equal to one, incoming tpbias is detected. disabled 1 rw 0 if equal to one, the port is disabled. negotiated_speed 3 r 000 indicates the maximum speed negotiated between this phy port and its immediately connected port; the encoding is the same as for they phy re gister max_speed field. int_enable 1 rw 0 enable port event inte rrupts. when set to one, the phy will set port_event to one if any of connected, bias, disabled, or fault (for this port) change state. fault 1 rw 0 set to one if an error is detected during a suspend or resume operation. a write of one to this bit clears it to zero.
24 agere systems inc. data sheet january 2005 two-cable transcei ver/arbiter device fw802bf phy 1394a-2000 internal register configuration (continued) the vendor identification page is used to identify the phy?s vendor and compliance level. the page is selected by writing one to page_select in the phy register at address 0111 2 . the format of the vendor identification page is shown in table 13; reserved fields are shown shaded. table 13. phy register page 1: vendor identification page the meanings of the register fields within the ve ndor identification page are defined by table 14. table 14. phy register vendor identification page fields the vendor-dependent page provides access to inform ation used in manufacturing test of the fw802bf. address contents bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1000 2 compliance_level 1001 2 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx 1010 2 1011 2 vendor_id 1100 2 1101 2 1110 2 product_id 1111 2 required xxxxx reserved field size type description compliance_level 8 r standard to which the phy implementation complies: 0 = not specified 1 = ieee 1394a-2000 agere?s fw802bf compliance level is 1. all other values reserved for future standardization. vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy. agere?s vendor id is 00601d 16 . this number is obtained from the ieee registration authority committee (r ac). the most significant byte of vendor_id appears at phy register location 1010 2 and the least significant at 1100 2 . product_id 24 r the meaning of this number is det ermined by the company or organization that has been granted vendor_id. agere?s fw802bf product id is 080201 16 . the most significant byte of product_id appears at phy register location 1101 2 and the least significant at 1111 2 .
agere systems inc. 25 data sheet january 2005 two-cable transceiver/arbiter device fw802bf phy 1394a-2000 outline diagrams 48-ball vtfsbgac dimensions are in millimeters. ordering information device code package comcode FW802BF-09-DB 48-ball vtfsbgac 700050786 note: 1. global plane is best fit plane as determined by coplanarity measurement equipment. 2. this package configuration has solder mask defined bga pads (smd). for details see indi- vidual substrate drawings (bottom view). 3. the solder ball diameter before reflow = 0.30 mm +0.10/-0.05 mm. pkg type a b c fsbga 0.36 ref 0.70 0.05 1.28 0.18 tfsbga 0.21 ref 0.70 0.05 1.13 0.13 vtfsbga 0.21 ref 0.45 0.03 0.88 0.10 detail a bottom view top view
agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are trademarks of agere systems inc. copyright ? 2005 agere systems inc. all rights reserved january 2005 ds05-046cmpr (replaces ds03-081cmpr-2) for additional information, contact your a gere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gate way, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 296 400 the i.link logo is a trademark and i.link is a registered trademark of sony corporation. ieee is a registered trademark of the institute of electrical and electr onics engineers, inc. the firewire logo is a trademark and firewire is a registered trademark of apple computer, inc.

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